The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a high-performance semiconductor structure including a bi-layer embedded epitaxy semiconductor source region and drain region.
Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance. For example, in common silicon technology, hole mobility is enhanced when the channel is under compressive stress, while the electron mobility is enhanced when the channel is under tensile stress. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to form embedded silicon germanium (SiGe) or silicon carbon (Si:C) stressors within the source and drain regions of a complementary metal oxide semiconductor (CMOS) device to induce compressive or tensile strain in the channel region located between the source region and the drain region. There are two common techniques that are employed in the semiconductor industry to form such embedded stressors. The first technique, which can be referred to as a late embedded stressor process, forms an in-situ doped stressor material after extension formation. While this late embedded stressor process provides stress conservation and lower source/drain resistance, the process provides a FET that exhibits poor short channel effects due to the formation of deep and heavily doped source and drain regions. The second technique that is commonly used is an early embedded stressor process in which an undoped epitaxy stressor material is formed prior to performing an extension ion implantation. Although this technique provides improved stress proximity to the device channel, it exhibits stress relaxation by performing the extension ion implantation at this stage of the process. Also, this technique requires complicated first spacers, and has a compatibility issue with high k/metal gate stacks.
Despite these advances in the semiconductor industry, further improvement in embedded stressor technology is needed that provides a good balance between stressor proximity and short channel effects.